This application claims the benefit of Korean Patent Application No. 71889/1997, filed Dec. 22, 1997, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a manufacturing method of a copper interconnection layer for a semiconductor device.
2. Discussion of the Related Art
Generally, aluminum (Al) has been used as a conventional interconnection layer for semiconductor devices due to its ease of use in a manufacturing process and low contact resistance. However, as semiconductor devices have become more highly integrated, the length of an interconnection line has become longer while its width has become narrower. Consequently, the resistance of the interconnection line increases. Also, more highly integrated semiconductor devices have an insulation film with a reduced thickness and with increased parasitic capacitance.
A number of studies have explored using metals with lower resistance compared to Al and having good electromigration properties for the interconnection of semiconductor devices. Copper has been considered as a new interconnection material for semiconductor devices. Copper has a relatively low specific resistivity (approximately 1.67 .mu..OMEGA./Cm) and excellent electromigration properties. Also, copper will not reduce the operational speed of the semiconductor device even if the cross-sectional area of the interconnection is reduced.
A conventional manufacturing method of a copper interconnection will now be described in detail with reference to the accompanying drawings.
FIGS. 1-5 illustrate the conventional manufacturing method of the copper interconnection for the semiconductor device.
As shown in FIG. 1, a gate electrode 2 is formed on an upper surface of a semiconductor substrate 1, and an n+ or p+ diffusion layer 3 is formed inside the semiconductor substrate 1 at both sides of the gate electrode 2. A first insulation layer 4 is applied over the diffusion layer 3 and the gate electrode 2, a bit line 5 is formed on the insulation layer 4, and a second insulation layer 6 is deposited on the bit line 5. Grooves a, b, and c are formed on surfaces of the diffusion layer 3, the gate electrode 2, and the bit line 5 in order to connect to an interconnection layer (formed later). A first barrier layer 7 (a contact layer) is formed at the sidewalls and bottoms of the grooves a, b, c, and on an upper surface of the second insulation layer 6. The first barrier layer 7 includes at least one of Ti, TiN, TaN, TiW, TaW, TiSi.sub.x Y.sub.y or TaSi.sub.x Y.sub.n film.
As shown in FIG. 2, a copper layer 8 is formed on the first barrier layer 7 by chemical vapor deposition (CVD), sputtering, ion cluster beam deposition (ICBD), or electroplating. An incubation time of forming the copper layer 8 in the grooves a, b, c is longer than that of forming the copper layer 8 on the insulation layer 6. Thus, incubation time should be determined in accordance with the incubation time of forming the copper layer 8 in the grooves a, b, c. Also, each portion of the copper layer 8 formed in the grooves a, b, c should be thicker than each portion of the copper layer 8 formed on the upper surface of the second insulation layer 6. An overall time of forming the copper layer 8 is determined by a time of forming the portion of the copper layer 8 in the grooves a, b, c. Accordingly, the time required to form the copper layer 8 increases. A second barrier layer 9 serving as a diffusion barrier is formed on the copper layer 8. The second barrier layer 9 includes at least one of Ti, TiN, TiW, TaN, TaW, TiSi.sub.x Y.sub.y, or TaSi.sub.x Y.sub.n. film.
As shown in FIG. 3, a photoresist film (not shown) is applied over the second barrier layer 9 and patterned, forming a photoresist mask 10. Using the photoresist mask 10, the first barrier layer 7, the copper layer 8, and the second barrier layer 9 are etched as shown in FIG. 4, forming a sandwich pattern 11 including the remaining first barrier layer 7, the copper layer 8, and the second barrier layer 9.
As shown in FIG. 5, to form a diffusion barrier on each sidewall of the sandwich pattern 11, a third barrier layer (not shown) is formed on an upper surface of the semiconductor device shown in FIG. 4, and an etch-back process is performed on the third barrier layer, forming a sidewall spacer 12. The third barrier layer remains on each sidewall of the sandwich pattern 11. The third barrier layer includes at least one of Ti, TiN, TiW, TaN, TaW, TiSi.sub.x Y.sub.y or TaSi.sub.x Yfilm.
The conventional copper layer 8 having low specific resistivity and excellent electromigration properties is capable of maintaining the operational speed and reliability of the semiconductor device despite a small cross-sectional area of the interconnection. Applying CVD thereto using an organic compound allows for a simple manufacturing process. However, the conventional copper layer 8 easily oxidizes and rapidly diffuses in silicon or insulating material.
In addition, in the conventional manufacturing method of the copper layer 8, a dry-etching process of the copper layer 8 is required to form the interconnection. However, the dry-etching process of a copper thin film has not been developed yet.
Also, the incubation time of forming the copper layer by CVD is long, resulting in a low manufacturing throughput.